cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 109

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.3.1.2
Table 5-18. Interrupt Status Register
28560-DSH-001-B
30:16
14:0
Bit
31
15
WRPTR 14:0]
RDPTR[14:0]
Field Name
MSTRABT
INTFULL
Host Access
Interrupt Status Register
The interrupt status register is located in a fixed position in the CX28560’s internal
register. The CX28560 updates this register after each transfer of interrupt descriptors
from its internal queue to the Interrupt Queue in shared memory. The host is required
to read this register from the CX28560 before it processes any interrupts. The contents
of the interrupt status register are reset on hardware reset or soft chip reset or
whenever any field in the Interrupt Queue Register is modified.
NOTE:
R/W
R
R
R
This internal register is directly accessed by the host.
Mindspeed Technologies™
Value
—
—
—
0
1
Advance Information
Master Abort.
When the CX28560 encounters a PCI abort while operating as a PCI
master, it does not attempt to recover from this error. In this case the
CX28560 asserts the SERR* signal, and the MSTRABT bit and waits for
the host to reset (i.e., PCI reset or Soft reset). This bit is asserted when
the target does not assert DEVSEL within a specific PCLK cycles or when
the target terminates a transaction in which the CX28560 is the master,
with an abort (i.e., assertion of STOP# with a deassertion of DEVSEL)
sequence.
Write Interrupt Pointer.
15-bit Quadword index from start of Interrupt Queue up to where the
CX28560 is going to insert the next Interrupt Descriptors. The host may
read this value to get the location of the last descriptor, which was not
served yet, in the queue. As the queue is circular, care must be taken to
ensure roll over at beginning and end of queue. Only the CX28560
updates this value. The WRPTR is a read only bit field.
Interrupt Queue Not Full—shared memory.
Interrupt Queue Full—shared memory.
The host writing ANY value to the RDPTR clears the INTFULL status bit.
Read Interrupt Pointer.
15-bit Quadword index from start of Interrupt Queue up to where the host
first unread Interrupt Descriptor resides. The host may read this value to
get the location of the first descriptor, which was not served yet, in the
queue. As the queue is circular, care must be taken to ensure roll over at
beginning and end of queue. Only the host updates this value. The RDPTR
is a read/write bit field.
NOTE(S):
INTFULL status bit. Therefore, if the value written into RDPTR is the same
value as was read from this field, it is assumed that the host has read all
the interrupt descriptors.
Writing the value of the RDPTR automatically resets the
Description
The CX28560 Memory Organization
5
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19