cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 242

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cx28560

Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
TSBUS
D.2.2
Figure D-3. Payload Time Slot Bus Transmit Data (TSB_TDAT)
D-8
TSB_TDAT
TSB_CLK
Transmit Timing
Transmit Bit n
The TSBUS device operates as the master of the Transmit TSBUS, and the
CX28560 device responds as slave. The TSBUS generates clock, Frame sync
signal, and Stuff signal. CX28560 will generate Transmit data (TSB_TDAT) or
generate an all-1s Stuff pattern eight time slots after receiving an active Stuff
signal. The TSBUS will generate a Frame sync Strobe (TSB_STB) output
synchronously with the rising edge of TSB_CLK.
timing requirements for the Transmit.
target timing values are listed in
T
pwh
Mindspeed Technologies™
T
per
Advance Information
T
pwl
Transmit Bit n+1
T
s
T
h
Table
Figure D-3
D-4.
Transmit Bit n+2
illustrates the Stuff signal. The
Figure D-3
illustrates the
CX28560 Data Sheet
28560-DSH-001-B

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