cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 94

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

The CX28560 Memory Organization
Table 5-2. Indirect Register Map Address Accessible via Service Request Mechanism (2 of 2)
5-4
RSIU Time Slot/Group Map Pointer Allocation Register
RSIU Port Configuration Register
TBUFFC Counter Memory
TBUFFC Channel Configuration Register
TBUFFC Flexiframe Memory
TBUFFC Data FIFO Size Register
TBUFFC Flexiframe Control Register
TBUFFC Flexiframe Slot Time Register
TSLP Channel Status Register
TSLP Channel Configuration Register
TSIU TS/Group Map
TSIU Group Map
TSIU Group Map Pointers Register
TSIU Group State Register
TSIU Time Slot/Group Map Pointer Allocation Register
TSIU Port Configuration Register
Transmit POS-PHY Thresholds Register
Transmit POS-PHY Control Register
Receive POS-PHY Control Register
EBUS Configuration Register
Global Configuration Register
These registers need to be accessed through the Service Request Mechanism.
Register
It is critically important that upon channel activation internal registers must be
initialized. The CX28560 assumes the information is valid once a channel is
activated.
Mindspeed Technologies™
Advance Information
Access
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
09BFC0–09BFDF
09BFE0–09BFFF
0DC000–0DDFFF
0DF000–0DFFFF
0E0000–0E53FF
0E7FFC
0E7FFD
0E7FFE
128800–128FFF
129000–1297FF
16C000–16DFFF
16E000–16FFFF
170000–1701FF
170200–1703FF
173FC0–173FDF
173FE0–173FFF
0E7FF9
0E7FFF
00FFFF
1B4000
1B4001
Descriptor
(22 bits)
Address
1 Per Port
1 Per Port
4 Per Channel
2 Per Channel
21K Per Chip
1 Per Chip
1 Per Chip
1 Per Chip
1 Per Channel
1 Per Channel
8K Per Chip
8K Per Chip
1 Per Group (512)
1 Per Group (512)
1 Per Port
1 Per Port
1 Per Chip
1 Per Chip
1 Per Chip
1 Per Chip
1 Per Chip
Number of
Instances
CX28560 Data Sheet
28560-DSH-001-B
Reset
Value
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X