cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 239

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table D-3. System Side Interface: Overhead Time Slot Bus Frame
D.1.1
28560-DSH-001-B
DS1/E1 Framer No. 1-28
STS-12/STS-3/STM-1 Mapper
STS-12/STS-3/STM-1 Mapper
SONET/SDH SDS-1/AU-3 Mapper
SONET/SDH STS-1/AU-3 Mapper
SONET/SDH STS-1/AU-3 Mapper
Unused Communication Time Slots
Command Status Processor (CSP)
TSBUS Source/Destination
VSP Mapping of Intermixed Digital Level 2 Signals
The following Digital Level 2 signals can transport either DS1 or E1 signals: VTG,
TUG-2, and DS2. SONET, SDH, and PDH transport their respective Level 2 signals
in sets of seven Level 2 signals. This set of seven Level 2 signals can operate in mixed
mode where a portion of the seven Level 2 multiplexed signals transport DS1 signals
and the remainder transport E1 signals. Any given Level 2 signal in mixed mode can
only transport DS1 signals or E1 signals. It cannot transport both signals.
Table D-4
mixed set of seven VTGs, a mixed set of seven TUG-2s, or a mixed set of seven DS2s.
Each level 2 signal has a set of 3 or 4 related framers. All framers within a set must be
configured for the same type of signal. This prevents framers for different data paths
from multiplexing data into the same time slot.
There are four framers in a set for DS1, VT1.5, and VC-11 signals. There are three
framers in a set for E1, VT2.0, and VC-12 signals.
The types of Level 2 signals that can be mixed together are limited to the following
combinations:
1.
2.
3.
DS2 signals containing DS1 signals and the DS2 signals containing E1 signals.
VTG signals containing VT1.5, which contain DS1 signals and VTG signals
containing VT2.0, which contain E1 signals.
TUG-2 signals containing VC-11, which contain DS1 signals and VTG-2
signals containing VC-12, which contain E1 signals.
defines the mapping of DS1 and E1 signals when they are extracted from a
Mindspeed Technologies™
F-bit Data Link/Sa4 Bit Data Link
Regenerator Section Data Communication Channel
(DCCR) Bytes 1–3
Multiplex Section (Line) Data Communication Channel
(DCCM) Bytes 1–9
Path User Channel: F2
Path User Channel: F3
SPE/AU Path Overhead Nibble N1 (4 LSBs) Path Data
Channel/Bit Oriented or LAPD Tandem Connection
Future Use
TBUS Register Management
Overhead Data Communication Channel Mapped to Virtual Serial Port
Advance Information
Description
(VSP)
3.564 Mbps
Data Rate
6.48 Mbps
112 Kbps
194 Kbps
583 Kbps
64 Kbps
64 Kbps
32 Kbps
TSBUS
D
-
5