cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 268

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cx28560

Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
Example of an Arbitration for Fast and Non-Fast Back-to-Back Transactions
Figure G-2. PCI Burst: Two 32-bit Transactions
G-2
C/BE#[3:0]
DEVSEL#
FRAME#
AD[31:0]
TRDY#
IRDY#
PAR
CLK
Bus Cmd
Address
Figure G-2
a burst read of 2 dwords transfer during the first cycle and 3 dwords transfer
during the second cycle. The fast back-to-back feature is disabled. It can be
observed that the first cycle takes 5 PCLK cycles (with one PCLK post-data
phase) and the second cycle of transferring 3 dwords requires 6 PCLK cycles.
BE1
Data1
Mindspeed Technologies™
illustrates how CX28560 operates at 32-bit address-data and performs
Data2
BE2
Advance Information
Bus Cmd
Address
BE1
Data1
Data2
BE2
Data3
BE3
CX28560 Data Sheet
28560-DSH-001-B

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