cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 195

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Figure 8-15. Transmit and Receive Channelized Non-T1 (i.e., N x 64) Mode
28560-DSH-001-B
LEGEND:
NOTE(S):
1. E1 Mode employs 32 time slots (0–31) with 8 bits per time slot (0–7) and 256 bits per frame and one frame every 125 µs
2. 2xE1 Mode employs 64 time slots (0–63) with 8 bits per time slot (0–7) and 512 bits per frame and one frame every 125
3. 4xE1 Mode employs 128 time slots (0–127) with 8 bits per time slot (0–7) and 1024 bits per frame and one frame every
4. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period.
5. CX28560 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge
6. Relationships between the various configurations of active edges for the synchronization signal and the data signal are
7. All received signals (e.g., RSYNC, RDAT, TSYNC) are sampled in on the specified clock edge (e.g. RCLK, TCLK). All
8. In configuration (a), synchronization and data signals are sampled/latched on a rising clock edge.
9. In configuration (b), synchronization signal is sampled on a rising clock edge and the data signal is sampled/latched on a
10. In configuration (c), synchronization signal is sampled on a falling clock edge and the data signal is sampled/latched on a
11. In configuration (d), synchronization and data signals are sampled/latched on a falling clock edge.
12. In TSBUS mode, the timing is identical to that in non-T1 mode. In order to convert the above diagram to TSBUS mode, the
(2.048 MHz).
µs (4.096 MHz).
125 µs (8.192 MHz).
independently of any other signal sampling configuration.
shown using a common clock signal for receive and transmit operations. Note the relationship between the frame bit
(within RDAT, TDAT) and the frame synchronization signal (e.g. RSYNC, TSYNC).
transmit data signals (TDAT) are latched on the specified clock edge.
falling clock edge.
rising clock edge.
names of the signals should be replaced as described in
ports (RGSYNC and TGSYNC) behave in an identical manner to RDAT and TDAT respectively.
M = N∞8 bits, where M = number of time slots.
RSYNC-RISE(a)
RSYNC-RISE(b)
RSYNC-FALL(d)
RSYNC-FALL(c)
TSYNC-RISE(a)
TSYNC-FALL(d)
TSYNC-RISE(b)
TSYNC-FALL(c)
RDATA-RISE(a)
RDATA-RISE(c)
TDATA-FALL(b)
TDATA-FALL(d)
RDAT-FALL(b)
RDAT-FALL(d)
TDAT-RISE(a)
TDAT-RISE(c)
RCLK
TCLK
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Advance Information
Chapter
1.0, Pin Descriptions. The additional 2 pins in the first 12
Electrical and Mechanical Specification
8
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