cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 39

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
Table 1-7. With DS0 extraction Mode Additional Pins (12 Ports Only)
Table 1-8. CX28560 POS-PHY Interface (Transmit) (1 of 2)
28560-DSH-001-B
TGSYNC[11:0]
RGSYNC[11:0]
TFCLK
TERR
TENB
TDAT[31:0]
TMOD[1:0]
TSOP
TEOP
Pin Name
Pin Name
I/O
I
I
I
I
I
I
I
I/O
O
I
—
TFCLK
TFCLK
TFCLK
TFCLK
TFCLK
TFCLK
Ref Clk
Table 1-8
TCLK[11:0]
RCLK[11:0]
Ref Clk
describes data transfer from the system to the CX28560.
Transmit FIFO Write Clock. TFCLK synchronizes data transfer transactions between the
system and the CX28560. TFCLK cycles at a rate of 100 MHz. Other signals are sampled
on the rising edge of this signal.
Transmit Error Indicator signal. TERR indicates that the current packet should be
aborted. When TERR is set high, the current packet is aborted. TERR should only be
asserted when TEOP is asserted.
Transmit Write Enable (TENB) signal. The TENB signal controls the flow of data to the
transmit FIFOs. When TENB is high, the TDAT, TMOD, TSOP, TEOP, and TERR signals
are invalid and are ignored by the CX28560. When TENB is low, the TDAT, TMOD, TSOP,
TEOP, and TERR signals are valid and are processed by the CX28560.
Transmit Packet Data Bus. This bus carries the packet octets that are written to the
CX28560’s FIFO. The TDAT bus is considered valid only when TENB is asserted. Data
must be transmitted in big endian order on TDAT[31:0]. In accordance with the HDLC
protocol, bit 0 of each byte is transmitted first.
Transmit Word Modulo signal. TMOD[1:0] indicates the number of valid bytes of data in
TDAT[31:0]. The TMOD[1:0] bus should always be all zero, except during the last
double-word transfer of a packet on TDAT[31:0]. When TEOP is asserted, the number
of valid packet data bytes on TDAT[31:0] is specified by TMOD[1:0].
TMOD[1:0] = 00 TDAT[31:0] valid
TMOD[1:0] = 01 TDAT[31:8] valid
TMOD[1:0] = 10 TDAT[31:16] valid
TMOD[1:0] = 11 TDAT[31:24] valid
Transmit Start of Packet (TSOP) signal. TSOP delineates the packet boundaries on the
TDAT bus. When TSOP is high, the start of the packet is present on the TDAT bus. TSOP
must be present at the beginning of every packet and is considered valid only when
TENB is asserted.
Transmit End of Packet (TEOP) signal. TEOP delineates the packet boundaries on the
TDAT bus. When TEOP is high, the end of the packet is present on the TDAT bus.
TMOD[1:0] indicates the number of valid bytes the last double word is composed of
when TEOP is asserted. TEOP must be present at the end of every packet and is
considered valid only when TENB is asserted.
Mindspeed Technologies™
Payload Time Slot Bus Transmit DS0 Sync (TGSYNC). When high, indicates that
data on TDATA is the first bit of the first group configured for the port of DS0
valid data.
Payload Time Slot Bus Receive DS0 Sync (RGSYNC). When high, indicates that
data on RDATA is the first bit of the first group configured for the port of DS0
valid data.
Advance Information
Description
Description
Introduction
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