cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 220

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Flexiframe Algorithm
B.2
B.3
B.3.1
B-2
New Flexiframe Required
Algorithm
Splitting Channel Bit Rates into Groups
The minimum number of system clock cycles (at 100 MHz) that each buffer
controller will spend on a given slot in the Flexiframe. The number of clock cycles
actually used will depend on the length of the fragment, the fact that 4 bytes are
transmitted per clock, and that after each fragment there is a break of 4 cycles before
the next fragment is started.
In the receive direction, if the fragment length register has a larger value than the slot
time or is less than 4 lower than the slot time, fragments will be transmitted with a gap
of 4 cycles between them. If the fragment length register is lower than the slot time by
more than 4, a fragment will be transmitted every slot time.
In the transmit direction, the system transmits fragments over the POS-PHY data bus
a maximum of once per slot time; if the fragment takes longer to transfer than the slot
time, the slot time is extended. Once per slot time, a channel number is read from the
Flexiframe, and an update report is sent to the system over the Flow Conductor POS-
PHY bus.
The maximum length of a Flexiframe is 21,504 entries. The actual length of the
Flexiframe produced by the algorithm should be written to the relevant register (see
Chapter
A new Flexiframe is required when one of the following is necessary:
To provide a software efficient algorithm, channels are organized into groups/tables
according to their bit rates and standard range definitions. This allows any channel bit
rate to be considered as one of a standard number (9) of bit rates. The standard range
definitions are based on a binary system, whereby each range limit is half the bit rate
of the previous limit.
For example, the fastest channel is of bit rate 52 Mbps, so the limits of the top group
are 52 Mbps and 26 Mbps. Any channel bit rate falling between these two limits will
be treated as if it is a channel of bit rate 52 Mbps. Any channel falling into the next
category (13 Mbps–26 Mbps) will be treated as a 26 Mbps channel, etc. The standard
limits are:
• Flexiframe length (Receive and Transmit)
• A new channel is to be activated
• Reset of the chip
#define LIMIT0_152
#define LIMIT1_226
#define LIMIT2_313
#define LIMIT3_46.5
#define LIMIT4_53.25
#define LIMIT5_61.625
#define LIMIT6_70.813
#define LIMIT7_80.406
#define LIMIT8_90.203
#define LIMIT9_100.101
5.0).
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B