cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 222

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Flexiframe Algorithm
B.3.3
B-4
Calculating Step Size Per Group
Assume that packet data is transferred in fragments of length FRAGLEN, and that the
receive direction the slot time register (see
words. The transfer of a packet of size (FRAGLEN + 1 words) will use the POS-PHY
and Flexiframe bandwidth usually occupied by 2 complete fragments. Hence in order
to withstand the bandwidth wastage caused in the worst case scenario of packets of
length FRAGLEN + 1, a channel should be serviced at a frequency that allows the
accumulation of 1/2 FRAGLEN worth of data.
If then this interval (STEPSIZE) is calculated for the first group (that which treats
each of its channels as if it were a 52 Mbps channel), this will provide the minimum
step size. Other step sizes are multiples of the minimum step size (due to binary
allocation).
For example, the fragment length is set in the register (see
fragment is of length 32 bytes), and the slot time is set to be 20 system clock cycles
(200 ns). The gap between each service of a 52 Mbps channel is calculated according
to the number of slots it will take the channel to accumulate 28 B of data. This amount
of time is 4307 ns, which is the equivalent of 430 clock cycles. Each clock cycle is
200 ns, hence the number of slots between services for a 52 Mbps channel is 21. Due
to the binary allocation, it is then simple mathematics that a channel in the next group
down requires servicing every 42 slots (2 * 21), etc.
Table B-1. The Flexiframe Structure
Mindspeed Technologies™
Track 2
Advance Information
Block m
Block 1
Block 2
...
Chapter
5.0) is set to FRAGLEN + 4
1
2
3
4
..
n
1
2
3
4
..
n
1
2
3
4
..
n
1
2
3
4
..
n
Min
Step
Size
Chapter
Slot
5.0) as 14, (each
CX28560 Data Sheet
28560-DSH-001-B
101302_013