PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 189

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 46
Register
LOOP
XSW
XSP
TSWM
XC0
XC1
RC0
RC1
IDLE
ICB(4:1)
LIM0
LIM1
PCD
PCR
XPM(2:0)
IMR(5:0)
RTR(4:1)
TTR(4:1)
TSS2
TSS3
GCR
CMR1
CMR2
PC(4:1)
PC5
PC6
MODE
MODE2
MODE3
Data Sheet
Reset Value Meaning
00
00
00
00
00
9C
00
9C
00
00
00
00
00
00
40
FF
all 00
all 00
00
00
00
00
00
00
00
00
00
00
00
00
Initial Values after Reset (E1) (cont’d)
H
H
H
H
H
H
H
H
H
H
H
H
H,
H
H
H
H
H
H,
H,
H
H
H
H
H
H
H
H
03
00
00
H
H
H
H
H
, 7B
H
Channel loop-back and single frame mode are disabled.
All bits of the transmitted service word are cleared. Spare
bit values are cleared.
No transparent mode active.
The transmit clock offset is cleared.
The transmit time slot offset is cleared.
The receive clock slot offset is cleared.
The receive time slot offset is cleared.
Idle channel code is cleared.
Normal operation (no “Idle Channel” selected).
Slave Mode, local loop off
Analog interface selected, remote loop off
Pulse count for LOS detection cleared
Pulse count for LOS recovery cleared
Transmit pulse mask (transmitter in tristate mode)
All interrupts are disabled
No time slots selected
Internal second timer, power on
RCLK output: DPLL clock, DCO-X enabled, DCO-X
internal reference clock
SCLKR selected, SCLKX selected, receive
synchronization pulse sourced by SYPR, transmit
synchronization pulse sourced by SYPX
Input function of ports RP(A to D): SYPR,
Input function of ports XP(A to D): SYPX
SCLKR, SCLKX, RCLK configured to inputs,
XMFS active low, CLK1 and CLK2 pin configuration
Signaling controller disabled
189
Operational Description E1
FALC56 V1.2
PEB 2256
2002-08-27