PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 248

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

MAS
Line Interface Mode 1 (Read/Write)
Value after reset: 00
LIM1
CLOS =
RIL(2:0)
Data Sheet
CLOS
7
Master Mode
0 =
1 =
Clear data in case of LOS
0 =
1 =
Receive Input Threshold
Only valid if analog line interface is selected (LIM1.DRS = 0).
“No signal” is declared if the voltage between pins RL1 and RL2 drops
below the limits programmed by bits RIL(2:0) and the received data
stream has no transition for a period defined in the PCD register.
The threshold where “no signal” is declared is programmable by the
RIL(2:0) bits depending on bit LIM0.EQON.
Note: LIM1.RIL(2:0) must be programmed before LIM0.EQON = 1 is
set.
See DC characteristics for detail.
RIL2
H
undisturbedly on the line. Receiver and transmitter coding must
be identical. Operates in analog and digital line interface mode.
In analog line interface mode data is transferred through the
complete analog receiver.
Slave mode
Master mode on. Setting this bit the DCO-R circuitry is
frequency synchronized to the clock (2.048 MHz or 8 kHz, see
IPC.SSYF) supplied by SYNC. If this pin is connected to V
V
circuitry is centered and no receive jitter attenuation is
performed (only if 2.048 MHz clock is selected by resetting bit
IPC.SSYF). The generated clocks are stable.
Normal receiver mode, receive data stream is transferred
normally in long-haul mode
In long-haul mode received data is cleared (driven to low level),
as soon as LOS is detected
DD
RIL1
(or left open and pulled up to V
RIL0
248
JATT
DD
RL
internally) the DCO-R
FALC56 V1.2
DRS
E1 Registers
0
PEB 2256
2002-08-27
(37)
SS
or