PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 9

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

List of Figures
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Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Multiple E1/T1/J1 Link over Frame Relay . . . . . . . . . . . . . . . . . . . . . . 24
8-Channel E1/T1/J1-Interface to the ATM Layer . . . . . . . . . . . . . . . . . 25
Pin Configuration P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pin Configuration P-LBGA-81-1 (bottom view) . . . . . . . . . . . . . . . . . . 27
Pin Configuration P-LBGA-81-1 (top view) . . . . . . . . . . . . . . . . . . . . . 28
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 57
Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Receive Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Protection Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 72
Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . . 75
2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 77
CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . . 89
Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . . 99
2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . 101
System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . 105
SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 107
SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 107
RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . . 108
RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . . 108
Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . 109
Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . 110
SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 112
SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 112
Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Single Channel Loop-Back (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Receiver Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9
FALC56 V1.2
PEB 2256
2002-08-27
Page