PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 279

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Global Clock Mode Register 5 (Read/Write)
Value after reset: 00
GCM5
MCLK_LOW
PLL_M(4:0)
Note: Write operations to GCM5 initiate a PLL reset (see below).
Global Clock Mode Register 6 (Read/Write)
Value after reset: 00
GCM6
PLL_N(4:0)
Note: Write operations to GCM6 initiate a PLL reset (see below).
Data Sheet
MCLK_
LOW
7
7
Master Clock Range Low
0 =
1 =
PLL Dividing Factor M
For details see calculation formulas below.
PLL Dividing Factor N
For details see calculation formulas below.
H
H
Master clock frequency divided by (PLL_M+1) is greater than or
equal 1.5 MHz
Master clock frequency divided by (PLL_M+1) is less than 1.5
MHz
PLL_M
PLL_N
4
4
279
PLL_M
PLL_N
3
3
PLL_M
PLL_N
2
2
PLL_M
PLL_N
1
1
PLL_M
PLL_N
FALC56 V1.2
E1 Registers
0
0
0
0
PEB 2256
2002-08-27
(96)
(97)