PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 31

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 1
Pin
No.
11
54
55
57
Data Sheet
Ball
No.
E1
D9
C9
C7
Pin Definitions - Microprocessor Interface (cont’d)
Symbol
IM
CS
BHE/
BLE
INT
Input (I)
Output (O)
Supply (S)
I + PU
I + PU
I + PU
O/oD
Function
Interface Mode
The level at this pin defines the bus interface
mode:
A low signal on this input selects the Intel
interface mode. A high signal on this input
selects the Motorola interface mode.
Chip Select
A low signal selects the FALC
write operations. This allows to connect
multiple devices to a single data/address bus.
Bus High Enable (Intel bus mode)
If 16-bit bus interface mode is enabled, this
signal indicates a data transfer on the upper
byte of the data bus D(15:8). In 8-bit bus
interface mode this signal has no function and
should be tied to
Bus Low Enable (Motorola bus mode)
If 16-bit bus interface mode is enabled, this
signal indicates a data transfer on the lower
byte of the data bus D(7:0). In 8-bit bus
interface mode this signal has no function and
should be tied to
INTerrupt Request
INT serves as general interrupt request for all
interrupt sources. These interrupt sources can
be masked via registers IMR(5:0). Interrupt
status is reported via registers GIS (Global
Interrupt Status) and ISR(5:0).
Output characteristics (push-pull active low/
high, open drain) are determined by
programming register IPC.
(oD = open drain output)
31
V
V
DD
DD
or left open.
or left open.
Pin Descriptions
®
56 for read and
FALC56 V1.2
PEB 2256
2002-08-27