PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 39

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

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Table 4
Pin
No.
66
65
Data Sheet
Ball
No.
B6
A7
Pin Definitions - System Interface
Symbol
RDO
SCLKR
Input (I)
Output (O)
Supply (S)
O
I/O + PU
System Interface Receive
Function
Receive Data Out
Received data that is sent to the system
highway. Clocking of data is done with the
rising or falling edge (SIC3.RESR) of SCLKR
or RCLK, if the receive elastic store is
bypassed. The delay between the beginning of
time slot 0 and the initial edge of SCLKR (after
SYPR goes active) is determined by the values
of registers RC1 and RC0.
If received data is shifted out with higher (more
than 2.048/1.544 Mbit/s) data rates, the active
channel phase is defined by bits
SIC2.SICS(2:0). During inactive channel
phases RDO is cleared (driven to low level, not
tristate).
System Clock Receive
Working clock for the receive system interface
with a frequency of 16.384/8.192/4.096/2.048
MHz in E1 mode and 16.384/8.192/4.096/
2.048 MHz (SIC2.SSC2 = 0) or 12.352/6.176/
3.088/1.544 MHz (SIC2.SSC2 = 1) in T1/J1
mode. If the receive elastic store is bypassed,
the clock supplied on this pin is ignored,
because RCLK is used to clock the receive
system interface.
If SCLKR is configured to be an output, the
internal working clock of the receive system
interface sourced by DCO-R or RCLK is
output.
39
Pin Descriptions
FALC56 V1.2
PEB 2256
2002-08-27