PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 62

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 10
Clock Source
Receive Data
(2.048 Mbit/s on RL1/RL2, RDIP/
RDIN or ROID)
Receive Data
in case of LOS
DCO-R
The intrinsic jitter generated in the absence of any input jitter is not more than 0.035 UI.
In digital bipolar line interface mode the clock and data recovery requires HDB3 coded
signals with 50% duty cycle.
4.1.6
The HDB3 line code or the AMI coding is provided for the data received from the ternary
or the dual-rail interface. In case of the optical interface a selection between the NRZ
code and the CMI Code (1T2B) with HDB3 or AMI postprocessing is provided. If CMI
code is selected the receive route clock is recovered from the data stream. The CMI
decoder does not correct any errors. In case of NRZ coding data is latched with the
falling edge of signal RCLKI. The HDB3 code is used along with double violation
detection or extended code violation detection (selectable by FMR0.EXZE)). In AMI code
all code violations are detected. The detected errors increment the code violation
counter (16 bits length).
When using the optical interface with NRZ coding, the decoder is bypassed and no code
violations are detected.
The signal at the ternary interface is received at both ends of a transformer.
The E1 operating modes 75
or using special transformers with different transfer ratios in one package (using center
tap). This selection does not require changing transformers.
Data Sheet
Receive Line Coding (E1)
RCLK Output Selection (E1)
or 120
RCLK Frequency
2.048 MHz
(recovered clock)
constant high
2.048 MHz
(generated by DCO-R,
synchronized on SYNC)
2.048 MHz
8.192 MHz
are selectable by switching resistors in parallel
62
Functional Description E1
CMR1.
DCS
X
0
1
X
X
FALC56 V1.2
PEB 2256
2002-08-27
CMR1.
RS1/0
00
01
10
10
11