SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 117

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

On-Chip Peripheral Components
Flrst Configuration:
CMx Registers Assigned to the Compare Timer
Every CMx register switched to the compare timer as a time base operates in compare mode 0 and
uses a port 4 pin as an alternate output function (see table 7-8: Alternate Port Functions of the
CCU).
– Modulation Range in Compare Mode 0
In the general description of compare mode 0 (section 7.5.4) and in the description of the timer 2/
CCx register configuration (section 7.5.5.1) it was mentioned that a compare output is restricted in
its maximum or minimum duty cycle. There is always a time portion of 1/2
n
(at n-bit timer length)
which is left over. This "spike" may either appear when the compare register is set to the reload
value (limiting the lower end of the modulation range) or it may occur at the end of a timer period as
realized in this configuration. In a compare timer/CMx register configuration, the compare output is
set to a constant high level if the contents of the compare registers are equal to the reload register
(CTREL). The compare output shows a high level for one timer clock period when a CMx register
is set to 0FFFF H . Thus, the duty cycle can be varied from 0.xx% to 100% depending on the
resolution selected (see calculation example in section 7.5.5.1). Please refer to figure 7-50 where
the maximum and minimum duty cycle of a compare output signal is illustrated. One clock period of
the compare timer is equal to one machine state (= 2 oscillator periods) if the prescaler is off. Thus,
at 12-MHz operational frequency the spike is approx. 166.6 ns long.
– The "Timer Overflow Controlled" Loading
There is one great difference between a CMx register and the other previously described compare
registers: compare outputs controlled by CMx registers have no dedicated interrupt function. They
use a "timer overflow controlled loading" (further on called "TOC loading") to reach the same
performance as an interrupt controlled compare. To show what this "TOC loading" is for, it will be
explained more detailed in the following:
The main advantage of the compare function in general is that the controller’s outputs are precisely
timed by hardware, no matter which task is running on the CPU. This in turn means that the CPU
normally does not know about the timer count. So, if the CPU writes to a compare register only in
relation to the program flow, then it could easily be that a compare register is overwritten before the
timer had the chance to reach the previously loaded compare value. Hence, there must be
something to "synchronize" the loading of the compare registers to the running timer circuitry. This
could either be an interrupt caused by the timer circuitry (as described before) or a special hardware
circuitry.
Semiconductor Group
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