SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 120

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

The mentioned condition for TOC loading prevents such undesired behavior. lf the user writes the
high byte first then no TOC loading will happen before the low byte has been written - even if there
is a timer overflow in between. lf the user just intends to change the low byte of the compare latch
then the high byte may be left unaffected.
Summary of the above description of the TOC loading:
Initializing the Compare Register/Compare Latch Circuit
Normally when the compare function is desired the initialization program would just write to the
compare register (called ’register latch’). The compare latch itself cannot be accessed directly by a
move instruction, it is exclusively loaded by the timer overflow signal.
In some very special cases, however, an initial loading of the compare latch could be desirable. lf
the following sequence is observed during initialization then latches, the register and the compare
latch, can be loaded before the compare mode is enabled.
Semiconductor Group
– The CMx registers are - when switched to the compare timer - protected from direct loading
– Thus, the CPU has a full timer period to load a new compare value: there is no danger of
– When writing a 16-bit compare value, the high byte should be written first since the write-to-
– lf there was no write access to a CMx low byte then no TOC loading will take place.
– Because of the TOC loading, all compare values written to CMx registers are only activated
by the CPU. A register latch couple provides a defined load time at timer overflow.
overwriting compare values which are still needed in the current timer period.
low-byte instruction enables a 16-bit wide TOC loading at next timer overflow.
in the next timer period.
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On-Chip Peripheral Components