SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 67

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SAB80C517-M16

Manufacturer Part Number
SAB80C517-M16
Description
8-Bit CMOS Single-Chip Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
On-Chip Peripheral Components
lf either of these two conditions is not met the received frame is irretrievably lost. lf both conditions
are met, the stop bit goes into RB80/RB81, the 8 data bits go into S0BUF/S1BUF, and RI0/Rl1 is
activated. At this time, no matter whether the above conditions are met or not, the unit goes back
to looking for a 1-to-0 transition in RxD0/RxD1.
7.2.3.3 Mode 2, 9-Bit UART (Serial Interface 0)
Mode 2 is functionally identical to mode 3 (see below). The only exception is, that in mode 2 the
baud rate can be programmed to two fixed quantities: either 1/32 or 1/64 of the oscillator frequency.
Note that serial interface 0 cannot achieve this baud rate in mode 3. Its baud rate clock is generated
f
by timer 1, which is incremented by a rate of
/12. The dedicated baud rate generator of serial
OSC
interface 1 however is clocked by a
f
/2-signal and so its maximum baud rate is
f
/32.
OSC
OSC
7.2.3.4 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1)
Eleven bits are transmitted (through TxD0/TxD1), or received (through RxD0/RxD1): a start bit (0),
8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data
bit (TB80/TB81) can be assigned the value of 0 or 1. On reception the 9th data bit goes into RB80/
RB81 in S0CON/S1CON.
Figures 7-18 a) and b) show a functional diagram of the serial interfaces in mode 2 and 3 or
mode A, resp. and associated timing. The receive portion is exactly the same as in mode 1. The
transmit portion differs from mode 1 only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. The
"write to S0BUF/S1BUF" signal also loads TB80/TB81 into the 9th bit position of the transmit shift
register and flags the TX control unit that a transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus the bit times
are synchronized to the divide-by-16 counter, and not to the "write-to-S0BUF/S1BUF" signal).
The transmission begins with the activation of SEND, which puts the start bit to TxD0/TxD1. One
bit time later, DATA is activated which enables the output bit of transmit shift register to TxD0/TxD1.
The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th
bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data shift out to the
right, zeros are clocked in from the left. When TB80/TB81 is at the output position of the shift
register, then the stop bit is just left of the TB80/TB81, and all positions to the left of that contain
zeros.
Semiconductor Group
68

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