SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 129

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Read Sequence
Note:
Any write access to ARCON triggers a shift or normalize operation and therefore changes the
contents of registers MD0 to MD3 !
Figure 7-56
Register ARCON
Arithmetic control register. Contains control flags and the shift counter of the MDU. Triggers a shift
or a normalize operation in register MD0 to MD3 when being written to.
Bit
MDEF
MDOV
SLR
SC.4
SC.3
SC.2
SC.1
SC.0
Semiconductor Group
– The order in which the first three registers MD0 to MD2 are read is not critical
– The last read from MD3 determines the end of a whole shift or normalize procedure and
releases the error flag mechanism.
0EF H
MDEF MDOV
Function
Error flag.
Indicates an improperly performed operation. MDEF is set by hardware
when an operation is retriggered by a write access to MDx before the first
operation has been completed. MDEF is automatically cleared after
being read.
Overflow flag.
Exclusively controlled by hardware. MDOV is set by following events:
Shift direction bit.
When set, shift right is performed. SLR = 0 selects shift left operation.
Shift counter.
When preset with 00000 B , normalizing is selected. After operation SC.0
to SC.4 contain the number of normalizing shifts performed. When set
with a value
performed is determined by the count written to SC.0 to SC.4.
– division by zero
– multiplication with a result greater than 0FFFF H .
SLR
0, shift operation is started. The number of shifts
SC.4
130
SC.3
On-Chip Peripheral Components
SC.2
SC.1
SC.0
ARCON