SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 172
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SAB80C517-M16
Manufacturer Part Number
SAB80C517-M16
Description
8-Bit CMOS Single-Chip Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAB80C517-M16.pdf
(323 pages)
- Current page: 172 of 323
- Download datasheet (4Mb)
Subtraction
Multiplication
Division
Flags
Unless otherwise stated in the previous descriptions, the flags of PSW are affected as follows:
Semiconductor Group
– SUBB (subtract with borrow) subtracts the second source operand from the the first operand
– DEC (decrement) subtracts one (1) from the source operand and returns the result to the
– MUL performs an unsigned multiplication of the A register, returning a double byte result. A
– DIV performs an unsigned division of the A register by the B register; it returns the integer
– CY is set if the operation causes a carry to or a borrow from the resulting high-order bit;
– AC is set if the operation results in a carry from the low-order four bits of the result (during
– OV is set if the operation results in a carry to the high-order bit of the result but not a carry
– P is set if the modulo-2 sum of the eight bits in the accumulator is 1 (odd parity); otherwise P
(the accumulator), subtracts one (1) if CY is set and returns the result to A.
operand.
receives the low-order byte, B receives the high-order byte. OV is cleared if the top half of the
result is zero and is set if it is not zero. CY is cleared. AC is unaffected.
quotient to the A register and returns the fractional remainder to the B register. Division by
zero leaves indeterminate data in registers A and B and sets OV; otherwise, OV is cleared.
CY is cleared. AC remains unaffected.
otherwise CY is cleared.
addition), or a borrow from the high-order bits to the low-order bits (during subtraction);
otherwise AC is cleared.
from the bit, or vice versa; otherwise OV is cleared. OV is used in two’s-complement
arithmetic, because it is set when the signal result cannot be represented in 8 bits.
is cleared (even parity). When a value is written to the PSW register, the P bit remains
unchanged, as it always reflects the parity of A.
173
Instruction Set
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