SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 151

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

8
The SAB 80C517 provides 14 interrupt sources with four priority levels. Seven interrupts can be
generated by the on-chip peripherals (i.e. timer 0, timer 1, timer 2, compare timer, serial interfaces
0 and 1 and A/D converter), and seven interrupts may be triggered externally.
Short Description of the Interrupt Structure for Advanced SAB 80(C)515 Users
The interrupt structure of the SAB 80C517 has been mainly adapted from the SAB 80(C)515. Thus,
each interrupt source has its dedicated interrupt vector and can be enabled/disabled individually;
there are also four priority levels available.
In the SAB 80C517 two interrupt sources have been added:
In the SAB 80(C)515 the 12 interrupt sources are combined to six pairs; each pair can be
programmed to one of the four interrupt priority levels. In the SAB 80C517 the new interrupt sources
were added to two of these pairs, thus forming triplets; therefore, the 14 interrupt sources are
combined to six pairs or triplets; each pair or triplet can be programmed to one of the four interrupt
priority levels (see chapter 8.2)
Figure 8-1 gives a general overview of the interrupt sources and illustrates the request and control
flags described in the next sections. The priority structure and the corresponding control bits are
listed in section 8.2.
8.1
A common mechanism is used to generate the various interrupts, each source having its own
request flag(s) located in a special function register (e.g. TCON, IRCON, S0CON, S1CON).
Provided the peripheral or external source meets the condition for an interrupt, the dedicated
request flag is set, whether an interrupt is enabled or not. For example, each timer 0 overflow sets
the corresponding request flag TF0. lf it is already set, it retains a one (1). But the interrupt is not
necessarily serviced.
Now each interrupt requested by the corresponding flag can individually be enabled or disabled by
the enable bits in SFR’s IEN0, IEN1, IEN2 (see figure 8-2, 8-3 and 8-4). This determines whether
the interrupt will actually be performed. In addition, there is a global enable bit for all interrupts
which, when cleared, disables all interrupts independent of their individual enable bits.
Semiconductor Group
– Compare timer overflow interrupt
– Receive and transmit interrupt of serial interface 1
Interrupt System
Interrupt Structure
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Interrupt System