HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 133

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Boot Mode Execution Procedure: The boot mode execution procedure is shown below.
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9
10
Host confirms normal reception of bit rate
adjustment end indication, and transmits
After bit rate adjustment, chip transmits
After receiving H'55, chip transfers part
Chip measures low period of H'00 data
(H'FC00 to H'FF2F), then checks flash
Host transmits H'00 data continuously
Chip calculates bit rate and sets value
of program bytes (N) to be transferred
Chip transfers user program to RAM
one H'00 data byte to host to indicate
After confirming that all flash memory
Chip transfers user program to RAM,
then transmits one H'AA byte to host
bytes to be transferred (N = N – 1)
address H'FBE0 and executes user
Chip receives, as 2 bytes, number
Chip branches to RAM boot area
Set pins to boot mode for chip
Chip branches to RAM area
program transferred to RAM
data is H'FF, chip transmits
Chip calculates remaining
of boot program to RAM
and execute reset-start
memory user area data
one H'AA byte to host
at prescribed bit rate
transmitted by host
one H'55 data byte
end of adjustment
in bit rate register
to on-chip RAM
All data = H'FF?
end byte count
Transfer
N = 0?
Start
Figure 6.10 Boot Mode Operation Flowchart
YES
Yes
*1
memory blocks
Erase all flash
No
*2
No
*2
*3
1. Set the chip to boot mode and execute a reset-start.
2. Set the host to the prescribed bit rate (2400/4800/9600)
3. The chip repeatedly measures the low period at the
4. After SCI3 bit rate adjustment is completed, the chip
5. On receiving the one-byte data indicating completion of
6. After receiving H'55, the chip transfers part of the boot
7. The chip branches to the RAM boot program area
8. The chip transmits one H'AA byte. The host then
9. The chip writes the received user program sequentially to
10. The chip transmits one H'AA byte, then branches to on
Notes: 1. The size of the RAM area available to the user is
and have it transmit H'00 data continuously using a
transfer data format of 8-bit data plus 1 stop bit.
RXD pin and calculates the asynchronous
communication bit rate used by the host.
transmits one H'00 data byte to indicate the end of
adjustment.
bit rate adjustment, the host should confirm normal
reception of this indication and transmit one H'55 data
byte.
program to RAM areas H'FB80 to H'FBDF and H'FC00
to H'FF2F.
(H'FC00–H'FF2F) and checks for the presence of data
written in the flash memory. If data has been written in
the flash memory, the chip erases all blocks.
transmits the number of user program bytes to be
transferred to the chip. The number of bytes should be
sent as two bytes, upper byte followed by lower byte.
The host should then transmit sequentially the program
set by the user.
The chip transmits the received byte count and user
program sequentially to the host, one byte at a time, as
verify data (echo-back).
on-chip RAM area H'FBE0 to H'FF6D (910 bytes).
-chip RAM address H'FBE0 and executes the user
program written in area H'FBE0 to H'FF6D.
2. The part of the user program that controls the
3. If a memory cell does not operate normally and
910 bytes. The number of bytes to be
transferred must not exceed 910 bytes. The
transfer byte count must be sent as two bytes,
upper byte followed by lower byte.
Example of transfer byte count: for 256 bytes
(H'0100), upper byte = H'01, lower byte = H'00
flash memory should be set in the program in
accordance with the flash memory program/
erase algorithms described later in this section.
cannot be erased, the chip transmits one H'FF
byte as an erase error indication and halts the
erase operation and subsequent operations.