HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 310

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Serial Status Register (SSR)
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7—Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been
transferred from TDR to TSR.
Bit 7: TDRE
0
1
304
Bit
Initial value
Read/Write
R/(W)*
TDRE
Description
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
Transmit data has not been written to TDR, or transmit data written in TDR has
been transferred to TSR
Setting conditions:
7
1
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
R/(W)*
RDRF
6
0
R/(W)*
OER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
R
2
1
MPBR
R
1
0
(initial value)
MPBT
R/W
0
0