HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 313

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 2—Transmit End (TEND): Bit 2 indicates that bit TDRE is set to 1 when the last bit of a
transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2: TEND
0
1
Bit 1—Multiprocessor Bit Receive (MPBR): Bit 1 stores the multiprocessor bit in a receive
character during multiprocessor format reception in asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1: MPBR
0
1
Note: * When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
Bit 0—Multiprocessor Bit Transfer (MPBT): Bit 0 stores the multiprocessor bit added to
transmit data when transmitting in asynchronous mode. The bit MPBT setting is invalid when
synchronous mode is selected, when the multiprocessor communication function is disabled, and
when not transmitting.
Bit 0: MPBT
0
1
affected and retains its previous state.
Description
Transmission in progress
Clearing conditions:
Transmission ended
Setting conditions:
Description
Data in which the multiprocessor bit is 0 has been received
Data in which the multiprocessor bit is 1 has been received
Description
A 0 multiprocessor bit is transmitted
A 1 multiprocessor bit is transmitted
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
*
(initial value)
(initial value)
(initial value)
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