HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 350

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

344
Internal
basic clock
Receive data
(RXD)
Synchronization
sampling timing
Data sampling
timing
Consequently, the receive margin in asynchronous mode can be expressed as shown in
equation (1).
where
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
M = {0.5 – 1/(2
M = (0.5 –
Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode
0
8 clock pulses
2N
Start bit
1
) –
16)}
D – 0.5
16 clock pulses
N
100 [%] = 46.875%
7
– (L – 0.5) F
100
15 0
. . . . . . . . . . . . . . . . . . Equation (2)
. . . . . . . . . . . . . . . Equation (1)
D0
7
15 0
D1