HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 83

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.3.5
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt operation is described as follows.
If an interrupt occurs while the interrupt enable register bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is
accepted; if the I bit is 1, the interrupt request is held pending.
If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
External or
internal
interrupts
External
interrupts or
internal
interrupt
enable
signals
Interrupt Operations
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt controller
I
CCR (CPU)
Interrupt
request
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