HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 134

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8/3644F, H8/3643F, or
H8/3642AF measures the low period of the asynchronous SCI communication data transmitted
continuously from the host (figure 6.11). The data format should be set as 8-bit data, 1 stop bit, no
parity. The chip calculates the bit rate of the transmission from the host from the measured low
period (9 bits), and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
The host should confirm that this adjustment end indication has been received normally, and
transmit one H'55 byte to the chip. If reception cannot be performed normally, initiate boot mode
again (reset), and repeat the above operations. Depending on the host’s transmission bit rate and
the chip’s system clock oscillation frequency (f
rates of the host and the chip. To insure correct SCI operation, the host’s transfer bit rate should be
set to 2400, 4800, or 9600 bps*
oscillation frequency for which automatic adjustment of the chip’s bit rate is possible. Boot mode
should be used within this system clock oscillation frequency range*
Notes: 1. Only use a host bit rate setting of 2400, 4800, or 9600 bps. No other bit rate setting
2. Although the chip may also perform automatic bit rate adjustment with bit rate and
should be used.
system clock oscillation frequency combinations other than those shown in table 6.11,
a degree of error will arise between the bit rates of the host and the chip, and
subsequent transfer will not be performed normally. Therefore, only a combination of
bit rate and system clock oscillation frequency within one of the ranges shown in table
6.11 can be used for boot mode execution.
Figure 6.11 Measurement of Low Period in Transmit Data from Host
Start
bit
D0
Low period (9 bits) measured (H'00 data)
D1
1
. Table 6.11 shows typical host transfer bit rates and system clock
D2
D3
OSC
), there will be a discrepancy between the bit
D4
D5
D6
2
.
D7
High period
(1 or more
bits)
Stop
bit
125