HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 284

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 1—Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW.
This bit is always read as 1. Data written to this bit is not stored.
Bit 1: B0WI
0
1
Bit 0—Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed, generating
an internal reset signal. The internal reset signal generated by the overflow resets the entire chip.
WRST is cleared to 0 by a reset from the RES pin, or when software writes 0.
Bit 0: WRST
0
1
Timer Counter W (TCW)
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is ø/8192. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
276
Bit
Initial value
Read/Write
TCW7
Description
Bit 0 is write-enabled
Bit 0 is write-protected
Description
Clearing conditions:
Setting conditions:
When TCW overflows and an internal reset signal is generated
R/W
7
0
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
TCW6
R/W
6
0
TCW5
R/W
5
0
TCW4
R/W
4
0
TCW3
R/W
3
0
TCW2
R/W
2
0
TCW1
R/W
1
0
(initial value)
(initial value)
TCW0
R/W
0
0