HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 344

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HD6433640

Manufacturer Part Number
HD6433640
Description
H8/3644 Series Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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Figure 10.24 Example of Multiprocessor Data Reception Flowchart
Set bit MPIE to 1
OER + FER = 1?
OER + FER = 1?
and FER in SSR
and FER in SSR
Read bits OER
Read bits OER
Read bit RDRF
Read bit RDRF
Clear bit RE to
Continue data
Read receive
Read receive
data in RDR
data in RDR
RDRF = 1?
RDRF = 1?
reception?
0 in SCR3
Own ID?
in SCR3
in SSR
in SSR
Start
End
No
Yes
Yes
No
Yes
No
4
5
Yes
No
No
Yes
No
Yes
Receive error
processing
(A)
1.
2.
3.
4.
5.
Set bit MPIE to 1 in SCR3.
Read bits OER and FER in the serial
status register (SSR) to determine if
there is an error. If a receive error has
occurred, execute receive error processing.
Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR and compare it with this receiver's
own ID. If the ID is not this receiver's,
set bit MPIE to 1 again. When the RDR
data is read, bit RDRF is cleared to 0
automatically.
Read SSR and check that bit RDRF is
set to 1, then read the data in RDR.
If a receive error has occurred, read bits
OER and FER in SSR to identify the error,
and after carrying out the necessary error
processing, ensure that bits OER and FER
are both cleared to 0. Reception cannot be
resumed if either of these bits is set to 1.
In the case of a framing error, a break can
be detected by reading the value of the
RXD pin.

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