HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 262

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 5—Input Edge Select C (IEDGC): Bit 5 selects the rising or falling edge of the input capture
C input signal (FTIC).
Bit 5: IEDGC
0
1
Bit 4— Input Edge Select D (IEDGD): Bit 4 selects the rising or falling edge of the input capture
D input signal (FTID).
Bit 4: IEDGD
0
1
Bit 3—Buffer Enable A (BUFEA): Bit 3 selects whether or not to use ICRC as a buffer register
for ICRA.
Bit 3: BUFEA
0
1
Bit 2—Buffer Enable B (BUFEB): Bit 2 selects whether or not to use ICRD as a buffer register
for ICRB.
Bit 2: BUFEB
0
1
Bits 1 and 0—Clock Select (CKS1, CKS0): Bits 1 and 0 select one of three internal clock
sources or an external clock for input to FRC. The external clock is counted on the rising edge.
Bit 1: CKS1
0
1
254
Bit 0: CKS0
0
1
0
1
Description
Falling edge of input capture C is captured
Rising edge of input capture C is captured
Description
Falling edge of input capture D is captured
Rising edge of input capture D is captured
Description
ICRC is not used as a buffer register for ICRA
ICRC is used as a buffer register for ICRA
Description
ICRD is not used as a buffer register for ICRB
ICRD is used as a buffer register for ICRB
Description
Internal clock: ø/2
Internal clock: ø/8
Internal clock: ø/32
External clock: rising edge
(initial value)
(initial value)
(initial value)
(initial value)
(initial value)