ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 143
ATMEGA325-16AJ
Manufacturer Part Number
ATMEGA325-16AJ
Description
8-bit Microcontroller with In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATMEGA325-16AJ.pdf
(347 pages)
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Serial Peripheral
Interface – SPI
2570A–AVR–09/04
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer
between the ATmega325/3250/645/6450 and peripheral devices or between several
AVR devices. The ATmega325/3250/645/6450 SPI includes the following features:
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•
•
•
•
•
•
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Figure 65. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in Figure 66.
The system consists of two shift Registers, and a Master clock generator. The SPI Mas-
ter initiates the communication cycle when pulling low the Slave Select SS pin of the
desired Slave. Master and Slave prepare the data to be sent in their respective shift
Registers, and the Master generates the required clock pulses on the SCK line to inter-
change data. Data is always shifted from Master to Slave on the Master Out – Slave In,
MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After
each data packet, the Master will synchronize the Slave by pulling high the Slave Select,
SS, line.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
1. Refer to Figure 1 on page 2, and Table 26 on page 59 for SPI pin placement.
DIVIDER
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ATmega325/3250/645/6450
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