ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 91

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ATMEGA325-16AJ

Manufacturer Part Number
ATMEGA325-16AJ
Description
8-bit Microcontroller with In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
2570A–AVR–09/04
Table 47. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit cor-
responding to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 48 shows the COM0A1:0 bit functionality when the
WGM01:0 bits are set to a normal or CTC mode (non-PWM).
Table 48. Compare Output Mode, non-PWM Mode
Table 49 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 49. Compare Output Mode, Fast PWM Mode
Note:
Table 50 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to
phase correct PWM mode.
Mode
COM01
COM01
0
1
2
3
0
0
1
1
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case,
WGM01
(CTC0)
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 86 for more details.
0
0
1
1
COM00
COM00
0
1
0
1
0
1
0
1
WGM00
(PWM0)
0
1
0
1
Description
Normal port operation, OC0A disconnected.
Toggle OC0A on compare match
Clear OC0A on compare match
Set OC0A on compare match
Description
Normal port operation, OC0A disconnected.
Reserved
Clear OC0A on compare match, set OC0A at TOP
Set OC0A on compare match, clear OC0A at TOP
Timer/Counter
Mode of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
ATmega325/3250/645/6450
0xFF
0xFF
OCR0A
0xFF
TOP
(1)
(1)
Update of
OCR0A at
Immediate
TOP
Immediate
TOP
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
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