ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 151

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ATMEGA325-16AJ

Manufacturer Part Number
ATMEGA325-16AJ
Description
8-bit Microcontroller with In-System Programmable Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
USART0
Overview
2570A–AVR–09/04
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device. The main features are:
A simplified block diagram of the USART Transmitter is shown in Figure 69. CPU acces-
sible I/O Registers and I/O pins are shown in bold.
Figure 69. USART Block Diagram
Note:
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
1. Refer to Figure 1 on page 2, Figure 2 on page 3 and “Alternate Functions of Port E”
on page 63 for USART pin placement.
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
UDR (Receive)
UBRR[H:L]
(1)
ATmega325/3250/645/6450
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRC
XCK
TxD
RxD
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