ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 210

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

JTAG Interface and
On-chip Debug
System
Features
Overview
Test Access Port – TAP
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ATmega325/3250/645/6450
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The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
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A brief description is given in the following sections. Detailed descriptions for Program-
ming via the JTAG interface, and using the Boundary-scan Chain can be found in the
sections “Programming via the JTAG Interface” on page 274 and “IEEE 1149.1 (JTAG)
Boundary-scan” on page 216, respectively. The On-chip Debug support is considered
being private JTAG instructions, and distributed within ATMEL and to selected third
party vendors only.
Figure 97 shows a block diagram of the JTAG interface and the On-chip Debug system.
The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers
as the scan chain (Shift Register) between the TDI – input and TDO – output. The
Instruction Register holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers
used for board-level testing. The JTAG Programming Interface (actually consisting of
several physical and virtual Data Registers) is used for serial programming via the JTAG
interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip
debugging only.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology,
these pins constitute the Test Access Port – TAP. These pins are:
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JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
Extensive On-chip Debug Support for Break Conditions, Including
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
Testing PCBs by using the JTAG Boundary-scan capability
Programming the non-volatile memories, Fuses and Lock bits
On-chip debugging
TMS: Test mode select. This pin is used for navigating through the TAP-controller
state machine.
TCK: Test Clock. JTAG operation is synchronous to TCK.
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
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2570A–AVR–09/04