ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 78

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

External Interrupt Flag
Register – EIFR
Pin Change Mask Register 3 –
PCMSK3
78
(1)
ATmega325/3250/645/6450
• Bit 7– PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT30..24 pin triggers an interrupt request, PCIF3
becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
This bit is reserved bit in ATmega325/645 and will always be read as zero.
• Bit 6– PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2
becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
This bit is reserved bit in ATmega325/645 and will always be read as zero.
• Bit 5– PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 4– PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 6..0 – PCINT30..24: Pin Change Enable Mask 30..24
Each PCINT30..24-bit selects whether pin change interrupt is enabled on the corre-
sponding I/O pin. If PCINT30..24 is set and the PCIE3 bit in EIMSK is set, pin change
interrupt is enabled on the corresponding I/O pin. If PCINT30..24 is cleared, pin change
interrupt on the corresponding I/O pin is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PCIF3
7
R
0
–
R/W
7
0
PCINT30
R/W
PCIF2
6
0
R/W
6
0
PCINT29
R/W
PCIF1
R/W
5
0
5
0
PCINT28
PCIF0
R/W
R/W
4
0
4
0
PCINT27
R/W
0
3
R
3
–
0
PCINT26
R/W
R
2
–
0
2
0
PCINT25
R/W
R
1
–
0
1
0
PCINT24
INTF0
R/W
R/W
0
0
2570A–AVR–09/04
0
0
PCMSK3
EIFR