ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 185

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

USI Status Register – USISR
USI Control Register – USICR
2570A–AVR–09/04
Note that the corresponding Data Direction Register to the pin must be set to one for
enabling data output from the Shift Register.
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition
is detected. When output disable mode or Three-wire mode is selected, the flag is set
when the 4-bit counter is incremented.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one
to the USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-
wire mode.
A start condition interrupt will wake up the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to
0). An interrupt will be generated when the flag is set while the USIOIE bit in USICR and
the Global Interrupt Enable Flag are set. The flag will only be cleared if a one is written
to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two-
wire mode.
A counter overflow interrupt will wake up the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is
detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt
Flag. This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.
The flag is only valid when Two-wire mode is used. This signal is useful when imple-
menting Two-wire bus master arbitration.
• Bits 3..0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be
read or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external
clock edge detector, by a Timer/Counter0 Compare Match, or by software using USI-
CLK or USITC strobe bits. The clock source depends of the setting of the USICS1..0
bits. For external clock operation a special feature is added that allows the clock to be
generated by writing to the USITC strobe bit. This feature is enabled by write a one to
the USICLK bit while setting an external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
Bit
Read/Write
Initial Value
Bit
USISIF
R/W
7
0
7
USIOIF
R/W
6
0
6
USIPF
R/W
5
0
5
ATmega325/3250/645/6450
USIDC
R
4
0
4
USICNT3
R/W
3
0
3
USICNT2
R/W
2
0
2
USICNT1
R/W
1
0
1
USICNT0
R/W
0
0
0
USISR
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