ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 171

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

USART Control and Status
Register n C – UCSRnC
2570A–AVR–09/04
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-
mal port operation for the TxD pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxD port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
• Bit 6 – UMSELn: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 72. UMSEL Bit Settings
• Bit 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmit-
ter will automatically generate and send the parity of the transmitted data bits within
each frame. The Receiver will generate a parity value for the incoming data and com-
pare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will
be set.
Table 73. UPM Bits Settings
Bit
Read/Write
Initial Value
UPMn1
UMSELn
0
0
1
1
0
1
R
7
–
0
UMSELn
R/W
6
0
Mode
Asynchronous Operation
Synchronous Operation
UPMn1
UPMn0
R/W
5
0
0
1
0
1
ATmega325/3250/645/6450
UPMn0
R/W
4
0
USBSn
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
R/W
3
0
UCSZn1
R/W
2
1
UCSZn0
R/W
1
1
UCPOLn
R/W
0
0
UCSRnC
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