ATMEGA325-16AJ ATMEL [ATMEL Corporation], ATMEGA325-16AJ Datasheet - Page 198

• Manufacturer Part Number: ATMEGA325-16AJ
• Description: 8-bit Microcontroller with In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

Changing Channel or
Reference Selection
198
ATmega325/3250/645/6450
Figure 89. ADC Timing Diagram, Free Running Conversion
Table 85. ADC Conversion Time
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-
porary register to which the CPU has random access. This ensures that the channels
and reference selection only takes place at a safe point during the conversion. The
channel and reference selection is continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selection is locked to ensure a
sufficient sampling time for the ADC. Continuous updating resumes in the last ADC
clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the
conversion starts on the following rising ADC clock edge after ADSC is written. The user
is thus advised not to write new channel or reference selection values to ADMUX until
one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic.
Special care must be taken when updating the ADMUX Register, in order to control
which conversion will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If
the ADMUX Register is changed in this period, the user cannot tell if the next conversion
is based on the old or the new settings. ADMUX can be safely updated in the following
ways:
When updating ADMUX in one of these conditions, the new settings will affect the next
ADC conversion.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
1. When ADATE or ADEN is cleared.
2. During conversion, minimum one ADC clock cycle after the trigger event.
3. After a conversion, before the Interrupt Flag used as trigger source is
cleared.
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
Complete
One Conversion
11
Sample & Hold (Cycles
from Start of Conversion)
12
13
13.5
Next Conversion
1
1.5
Sign and MSB of Result
LSB of Result
2
2
MUX and REFS
Update
3
Sample & Hold
4
Conversion Time
(Cycles)
13.5
25
13
2570A–AVR–09/04