XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 113

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XC68HC705JJ7

Manufacturer Part Number
XC68HC705JJ7
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet

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MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
V–
V+
NOTE:
NOTE:
V
IO
Either comparator may generate an output flag when the inputs are
exchanged due to a change in the state of the INV bit. It is therefore
recommended that the INV bit not be changed while waiting for a
comparator flag. Further, any changes to the state of the INV bit should
be followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to
clear any extraneous CPF1 or CPF2 flags that may have occurred.
VREF
MUX1:4
The V
voltage generated by the total chip current passing through the package
bond wires and lead frame that are attached to the single V
offset raises the internal V
+
COMP
This read/write bit connects the channel select bus to V
a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown
in
These are read/write bits that connect the analog subsystem pins to
the channel select bus and voltage comparator 2 for purposes of
making a voltage measurement. They can be selected individually or
combined with any of the other input sources to the channel select
bus as shown in
Table
1 = Channel select bus connected to V
0 = Channel select bus cannot be connected to V
AOFF
INV = 0
Figure 8-4. INV Bit Action
RISE
WHEN
V+ > V–
voltage source shown in
8-2. This bit is cleared by a reset of the device.
Analog Subsystem
Table
SS
8-2.
reference (AV
V+
V–
Figure 8-1
SS
DD
) in the analog subsystem
if all MUX1:4 are cleared.
depicts a small offset
V
IO
Analog Multiplex Register
+
COMP
Advance Information
DD
Analog Subsystem
DD
.
INV = 1
SS
for making
RISE
WHEN
V+ > V–
pin. This
113

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