XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 116

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Analog Subsystem
Advance Information
116
ATD1–ATD2
ICEN
Disabled
Option
Mode
The ATD1–ATD2 enable bits select one of the four operating modes
used for making A/D conversions via the single-slope method.These
four modes are given in
ISEN enable bit is cleared. These bits are cleared by a reset of the
device and thereby return the analog subsystem to the manual A/D
conversion method.
This is a read/write bit that enables a voltage comparison to trigger the
input capture register of the programmable timer when the CPF2 flag
bit is set. Therefore, an A/D conversion could be started by receiving
an OCF or TOF from the programmable timer and then terminated
when the voltage on the external ramping capacitor reaches the level
of the unknown voltage. The time of termination will be stored in the
A/D
3
synchronized
source and
charge and
(OCF–ICF)
Automatic
discharge
discharge
disabled
Control
Charge
Current
to timer
Analog Subsystem
Table 8-3. A/D Conversion Options
ISEN
0
1
1
1
1
Table
ATD2 ATD1
A/D Options
X
0
1
1
1
MC68HC705JJ7 • MC68HC705JP7 — REV 4
8-3. These bits have no effect if the
X
0
0
1
1
CHG
X
1
1
0
1
Current control disabled,
no source or sink current
Begin sourcing current
when the CHG bit is set
and continue to source
current until the CHG bit
is cleared.
The CHG bit remains set
until the next time ICF
occurs.
The CHG bit remains
cleared until the next
time OCF occurs.
The CHG bit remains set
until the next time ICF
occurs.
to/from PB0/AN0
Current Flow
MOTOROLA