XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 69

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
NOTE:
Address:
Reset:
EPMSEC — EPROM Security
OPT — Optional Features Bit
See
descriptions of the OPT bit.
COPC — COP Clear Bit
The COP watchdog reset will assert the pulldown device to pull the
RESET pin low for three to four cycles of the internal bus.
The COP watchdog reset function can be enabled or disabled by
programming the COPEN bit in the MOR.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
Read:
Write:
copying the EPROM/OTPROM difficult for unauthorized users.
The EPMSEC bit is an EPROM, write-only security bit to protect the
contents of the user EPROM code stored in locations $0700–$1FFF.
The OPT bit enables two additional features: direct drive by
comparator 1 output to PB4 and voltage offset capability to sample
capacitor in analog subsystem.
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
8.8.1 Voltage Comparator 1
1 = Optional features enabled
0 = Optional features disabled
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
$1FF0
EPMSEC
Bit 7
U
Figure 5-2. COP and Security Register (COPR)
= Unimplemented
OPT
U
6
Resets
U
5
(1)
U = Unaffected
Bit
and
U
4
8.11 Sample and Hold
U
3
U
2
Advance Information
U
Internal Resets
1
for further
COPC
Resets
Bit 0
U
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