XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 162

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Programmable Timer
11.3 Timer Registers
Advance Information
162
The functional block diagram of the 16-bit free-running timer counter and
timer registers is shown in
transparent buffer latch on the LSB of the 16-bit timer counter.
The timer registers (TMRH and TMRL) shown in
read-only locations which contain the current high and low bytes of the
16-bit free-running counter. Writing to the timer registers has no effect.
Reset of the device presets the timer counter to $FFFC.
The TMRL latch is a transparent read of the LSB until a read of the
TMRH takes place. A read of the TMRH latches the LSB into the TMRL
location until the TMRL is again read. The latched value remains fixed
even if multiple reads of the TMRH take place before the next read of the
TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB
of the timer at TMRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
RESET
READ
TMRH
Figure 11-2. Programmable Timer Block Diagram
$FFFC
Programmable Timer
READ
$0012
TIMER CONTROL REG.
TMRH ($0018)
OVERFLOW (TOF)
Figure
LATCH
16-BIT COUNTER
MC68HC705JJ7 • MC68HC705JP7 — REV 4
11-2. The timer registers include a
TMRL ($0019)
TMR LSB
TIMER STATUS REG.
Figure 11-3
$0013
4
MOTOROLA
are
INTERNAL
INTERRUPT
(OSC
READ
TMRL
REQUEST
INTERNAL
CLOCK
TIMER
DATA
BUS
2)