XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 145

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

9.4 SIOP Registers
9.4.1 SIOP Control Register (SCR)
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Address:
The first data bit will be shifted out to the SDO pin on the first falling edge
of the SCK. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
The SIOP control register (SCR) is located at address $000A and
contains seven control bits and a write-only reset of the interrupt flag.
Figure 9-4
value of each bit after reset.
SPIE — Serial Peripheral Interrupt Enable Bit
Reset:
Read:
Write:
The SPIE bit enables the SIOP to generate an interrupt whenever the
SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the
state of the SPIF flag bit and will not terminate a serial interrupt once
the interrupt sequence has started. Reset clears the SPIE bit.
1 = Serial interrupt enabled
0 = Serial interrupt disabled
$000A
SPIE
Simple Synchronous Serial Interface
Bit 7
0
shows the position of each bit in the register and indicates the
Figure 9-4. SIOP Control Register (SCR)
SPE
6
0
LSBF
5
0
MSTR
4
0
Simple Synchronous Serial Interface
SPIR
3
0
0
CPHA
2
0
Advance Information
SPR1
SIOP Registers
1
0
Figure
SPR0
Bit 0
0
9-3.
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