XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet - Page 71

• Manufacturer Part Number: XC68HC705JJ7
• Description: MICROCONTROLLER
• Manufacturer: Motorola

5.6.2 I/O Registers
5.6.3 Core Timer
5.6.4 COP Watchdog
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
A reset has these effects on input/output (I/O) registers:
A reset has these effects on the core timer:
A reset clears the COP watchdog timeout counter.
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices
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Clears bits in data direction registers configuring pins as inputs:
– DDRA5–DDRA0 in DDRA for port A
– DDRB7–DDRB0 in DDRB for port B
– DDRC7–DDRC0 in DDRC for port C
Clears bits in pulldown inhibit registers to enable pulldown
devices:
– PDIA5–PDIA0 in PDRA for port A
– PDIB7–PDIB0 in PDRB for port B
– PDICH and PDICL in PDRA for port C
Has no effect on port A, B, or C
Sets the IRQE bit in the interrupt status and control register (ISCR)
Clears the core timer counter register (CTCR)
Clears the core timer interrupt flag and enable bits in the core timer
status and control register (CTSCR)
Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1)
such that the device will start with the longest real-time interrupt
and longest COP timeout delays
Resets
(1)
data registers
(1)
(1)
Advance Information
Reset States
Resets
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