AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 194

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

31-0
Note: Bits 10-0 in this register are programmable
through the EEPROM.
Bit
31-11
10
9
8
7
194
RES
Name
RES
PME_EN_OVR
LCDET
PMAT
LCMODE
zeros and read as undefined.
zeros and read as undefined.
PME_EN Overwrite. When
bit is set and the MPMAT or LC-
DET bit is set, the PME pin will al-
ways be asserted regardless of
the state of PME_EN bit.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
set when the MII auto-polling log-
ic detects a change in link status
and the LCMODE bit is set.
This bit can be cleared to 0 either
by writing 1 to CSR116, bit 9 or by
writing 1 to STAT0, bit 10.
initially applied (POR).
When this bit is set to 1, the LC-
DET bit gets set when the MII
auto polling logic detects a Link
Change.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
when the PMMODE bit is set and
an OnNow pattern match occurs.
This bit can be cleared to 0 either
by writing 0 to CSR116, bit 7 or by
writing 1 to STAT0, bit 12.
Reserved locations. Written as
Reserved locations. Written as
Read/Write accessible. Cleared
Link Change Detected. This bit is
LCDET is cleared when power is
Read/Write accessible.
Link Change Wake-up Mode.
Read/Write accessible. Cleared
Pattern Matched. This bit is set
Description
P R E L I M I N A R Y
this
Am79C976
6
5
4
EMPPLBA
MPMAT
MPPEN
Read/Write
EMPPLBA
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
This bit can be cleared to 0 either
by writing 0 to CSR116, bit 5 or by
writing 1 to STAT0, bit 11.
initially applied (POR).
Broadcast Accept. If both EMP-
PLBA and MPPLBA (CSR5, bit 5)
are at their default value of 0, the
Am79C976 controller will only de-
tect a Magic Packet frame if the
destination address of the packet
matches the content of the physi-
cal address register (PADR). If ei-
ther EMPPLBA or MPPLBA is set
to 1, the destination address of
the Magic Packet frame can be
unicast, multicast, or broadcast.
Note that the setting of EMPPL-
BA and MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
gardless
destination address it has.
set when PCnet-FAST+ detects a
Magic Packet while it is in the
Magic Packet mode.
initially applied (POR).
this bit is set, the device enters
the Magic Packet mode when the
PG input goes LOW or MPEN bit
(CSR5, bit 2) gets set to 1. This
bit is OR’ed with MPEN (CSR5,
bit 2).
by H_RESET and is not affected
PMAT is cleared when power is
Read/Write accessible.
Magic Packet Physical Logical
Magic Packet Match. This bit is
MPMAT is cleared when power is
Read/Write accessible.
Magic Packet Pin Enable. When
Read/Write accessible. Cleared
of
is
what
set
accessible.
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