AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 74
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 74 of 309
- Download datasheet (3Mb)
rectly into PCI memory space and can not be accessed
indirectly through the RAP and RDP registers.
To simplify the use of software debuggers, the counter
logic is designed so that the statistics counters can be
accessed one, two, or four bytes at a time. When a por-
tion of a statistics counter is read, the entire 32 bits of
the counter is loaded into an internal holding register in
a single atomic operation. When the CPU reads one or
more bytes from the same counter, the data are read
from the holding register rather than from the counter.
The holding register is updated when either a read ac-
cess is made to a different counter or a byte of the
same counter is read for a second time.
Write access to statistics counters is provided for de-
bugging purposes only. No holding register is used for
write accesses. Writing one or two bytes at a time to a
statistics counter while the network is active can cause
unpredictable results.
The contents of the entire set of statistics counters can
be cleared to zero by setting the INIT_MIB bit (CMD3,
bit 25). The counters will be cleared within approxi-
mately 55 ERCLK cycles after the INIT_MIB bit is set.
The receive statistics counters are defined and the
Management Information Base (MIB) objects that they
support are listed in Table 7.
74
Offset (hex)
0C
00
04
08
RcvMissPkts
RcvOctets
RcvBroadCastPkts
RcvMultiCastPkts
Receive Counter Name
Table 7. Receive Statistics Counters
RMON etherStatsDropEvents
RMON etherHistoryDropEvents
MIB-II ifInDiscards
E-like
dot3StatsInternalMacReceiveErrors
RMON etherStatsOctets
RMON etherHistoryOctets
MIB-II IfInOctets
RMON etherStatsBroadcastPkts
RMON etherHistoryBroadcastPkts
EXT-MIB-II ifInBroadcastPkts
RMON etherStatsMulticastPkts
RMON etherHistoryMulticastPkts
EXT-MIB-II ifInMulticastPkts
P R E L I M I N A R Y
MIB Object Supported
Am79C976
For these counters, the definition of a valid frame de-
pends on the state of the JUMBO and VSIZE bits
(CMD3, bits 21 and 20) as follows:
If JUMBO = 1, valid frames are frames that are be-
tween 64 and 65536 bytes in length and have a correct
FCS value. Frames longer than 65536 bytes may not
be handled properly.
If JUMBO = 0 and VSIZE = 0, valid frames are frames
that are between 64 and 1518 bytes in length and have
a correct FCS value.
If JUMBO = 0 and VSIZE = 1, valid frames are frames
that are between 64 and 1522 bytes in length and have
a correct FCS value.
In Table 7, the Offset column gives the offset with re-
spect to the value stored in the read-only MIB Offset
register, which is located at offset 28h in the memory
address space allocated to the Am79C976 device. The
actual address of a particular counter is the sum of the
following quantities:
The number of times a receive packet was
dropped due to lack of resources. This is
the number of times a packet was dropped
due to receive FIFO overflow. This count
does not include undersize, oversize,
misaligned or bad FCS packets.
The total number of octets of data
received including octets from invalid
frames. This does not include the
preamble but does include the FCS bits.
The RcvOctets counter is incremented
whenever the receiver receives an octet.
The total number of valid frames received
that are addressed to a broadcast
address. This counter does not include
errored broadcast packets or valid
multicast packets.
The total number of valid frames received
that are addressed to a multicast address.
This counter does not include errored
multicast packets or valid broadcast
packets.
Description of Counter/Comments
8/01/00
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