AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 41

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

8/01/00
FRAME
IRDY
C/BE
REQ
GNT
CLK
C[3:0]
AD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write Invalidate
2
Command
3
4
ADDR
P R E L I M I N A R Y
CMD
Table 3. PCI Commands
22929B12
5
Not used
Not used
Not used
Not used
Read of the initialization block and descriptor rings
Read of the transmit buffer in non-burst mode
Write to the descriptor rings and to the receive buffer
Not used
Not used
Read of descriptor or transmit buffer in burst mode
Used when required
Read of descriptor or transmit buffer in burst mode
Burst write of 1 or more complete cache lines to the receive buffer
Am79C976
The Am79C976 controller typically performs more than
one non-burst read transaction within a single bus mas-
tership period. FRAME is dropped between consecu-
tive non-burst read cycles. REQ, however, stays
asserted until FRAME is asserted for the last transac-
tion. The Am79C976 controller supports zero wait-
state read cycles. It asserts IRDY immediately after the
address phase and at the same time starts sampling
DEVSEL. Figure 11 shows two non-burst read transac-
tions. The first transaction has zero wait states. In the
second transaction, the target extends the cycle by as-
serting TRDY one clock later.
The Am79C976 controller supports burst mode for all
bus master read operations. To allow burst transfers in
descriptor read operations, the Am79C976 controller
must be programmed to use SWSTYLE 3, 4, or 5
(BCR20, bits 7-0).
The BIU chooses which PCI command to use as fol-
lows:
When reading one DWord, use Memory Read.
When reading a block of more than one DWord that
does not cross a cache line, use Memory Read
Line.
When reading a block that crosses a cache line
boundary, use Memory Read Multiple.
Use
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