AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 69

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

If a collision is detected after 512-bit times have been
transmitted, the collision is termed a late collision. The
MAC engine will abort the transmission, append the
jam sequence, and increment the XmtLateCollision
counter. If RTRY_LCOL (CMD3, bit 16) is set to 1, the
retry logic treats late collisions just like normal colli-
sions. However, if the RTRY_LCOL bit is cleared to 0,
no retry attempt will be scheduled on detection of a late
collision. In this case, the transmit message will be
flushed from the FIFO.
The ISO 8802-3 (IEEE/ANSI 802.3) Standard requires
use of a “truncated binary exponential backoff” algo-
rithm, which provides a controlled pseudo random
mechanism to enforce the collision backoff interval, be-
fore retransmission is attempted.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
The Am79C976 controller provides an alternative algo-
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This aids in networks where large numbers of nodes
are present, and numerous nodes can be in collision. It
effectively accelerates the increase in the backoff time
in busy networks and allows nodes not involved in the
collision to access the channel, while the colliding
nodes await a reduction in channel activity. Once chan-
nel activity is reduced, the nodes resolving the collision
time-out their slot time counters as normal.
This modified backoff algorithm is enabled when EMBA
(CSR3, bit 3) is set to 1.
Transmit Operation
The transmit operation and features of the Am79C976
controller are controlled by programmable options. The
Am79C976 controller provides a large transmit FIFO to
provide frame buffering for increased system latency,
automatic retransmission with no FIFO reload, and au-
tomatic transmit padding.
Automatic transmit features such as retry on collision,
FCS generation/transmission, and pad field insertion
can all be programmed to provide flexibility in the (re-)
transmission of messages.
Disable retry on collision (DRTY) is controlled by the
DRTY bit of the Mode register (CSR15) in the initializa-
tion block.
8/01/00
“At the end of enforcing a collision (jamming), the
CSMA/CD sublayer delays before attempting to re-
transmit the frame. The delay is an integer multiple
of slot time. The number of slot times to delay be-
fore the nth retransmission attempt is chosen as a
uniformly distributed random integer r in the range:
0 £ r < 2
k
where k = min (n,10).”
P R E L I M I N A R Y
Am79C976
Automatic pad field insertion is controlled by the
APAD_XMT bit in CSR4.
The disable FCS generation/transmission feature can
be programmed as a static feature or dynamically on a
frame-by-frame basis.
REX_RTRY (CMD3, bit 18) and REX_UFLO (CMD3,
bit 17) can be programmed to cause the transmitter to
automatically restart the transmission process instead
of discarding a frame that experiences an excessive
collisions or underflow error. In this case the retrans-
mission will not begin until the entire frame has been
loaded into the transmit FIFO. The RTRY_LCOL bit
(CMD3, bit 16) can be programmed either to drop a
frame after a late collision or to treat late collisions just
like normal collisions.
Transmit FIFO Watermark (XMTFW) in CSR80 sets the
point at which the controller requests more data from
the transmit buffers for the FIFO. A minimum of
XMTFW empty spaces must be available in the trans-
mit FIFO before the controller will request the system
bus in order to transfer transmit frame data into the
transmit FIFO.
Transmit Start Point (XMTSP) in CSR80 sets the point
when the transmitter actually attempts to transmit a
frame onto the media. A minimum of XMTSP bytes
must be written to the transmit FIFO for the current
frame before transmission of the current frame will be-
gin. (When automatically padded packets are being
sent, it is conceivable that the XMTSP is not reached
when all of the data has been transferred to the FIFO.
In this case, the transmission will begin when all of the
frame data has been placed into the transmit FIFO.)
The default value of XMTSP is 01b, meaning there has
to be 64 bytes in the transmit FIFO to start a transmis-
sion.
In order to ensure that collisions occurring within 512-
bit times from the start of transmission (including pre-
amble) will be automatically retried with no host inter-
vention, the transmit FIFO ensures that data contained
within the FIFO will not be overwritten until at least 64
bytes (512 bits) of preamble plus address, length, and
data fields have been transmitted onto the network
without encountering a collision. If the REX_RTRY bit
or the REX_UFLO bit is set, the transmit data will not
be overwritten until the frame has been either transmit-
ted or discarded.
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble). This al-
lows the minimum frame size of 64 bytes (512 bits) for
IEEE 802.3/Ethernet to be guaranteed with no software
intervention from the host/controlling process. Setting
the APAD_XMT bit in CSR4 enables the automatic
padding feature. The pad is placed between the LLC
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