AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 54
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 54 of 309
- Download datasheet (3Mb)
Table 4 shows the descriptor read sequence. During
descriptor write accesses, only the byte lanes which
need to be written are enabled.
The settings of SWSTYLE (BCR20, bits 7-0) affect the
way the Am79C976 controller performs descriptor write
operations.
When SWSTYLE is set to 0 or 2, all descriptor write op-
erations are performed in non-burst mode.
When SWSTYLE is set to 3, 4, or 5, the descriptor en-
tr ies are ordered to allow burst transfers. The
Am79C976 controller will perform all descriptor write
operations in burst mode. See Table 5 for the descriptor
write sequence.
54
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
2
MD1
0110
3
PAR
4
0000
DATA
5
DATA
PAR
6
P R E L I M I N A R Y
22929B25
PAR
7
Am79C976
SWSTYLE
BCR20
[7:0]
0
2
3
4
5
Table 4. Descriptor Read Sequence
Address = XXXX
XX00h
Turn around cycle
Data
Idle
Address = XXXX
XX04h
Turn around cycle
Data
Address = XXXX
XX04h
Turn around cycle
Data
Idle
Address = XXXX
XX00h
Turn around cycle
Data
Address = XXXX
XX04h
Turn around cycle
Data
Data
Address = XXXX
XX04h
Turn around cycle
Data
Data
Address = XXXX
XX08h
Turn around cycle
Data
Data
Data
AD Bus Sequence
for Rx Descriptors
Address = XXXX
XX00h
Turn around cycle
Data
Idle
Address = XXXX
XX04h
Turn around cycle
Data
Address = XXXX
XX04h
Turn around cycle
Data
Idle
Address = XXXX
XX00h
Turn around cycle
Data
Address = XXXX
XX04h
Turn around cycle
Data
Data
Address = XXXX
XX00h
Turn around cycle
Data
Data
Data
Address = XXXX
XX00h
Turn around cycle
Data
Data
Data
Data
AD Bus Sequence
for Tx Descriptors
8/01/00
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